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MC74LVX573 Octal D-Type Latch with 3-State Outputs
With 5 V-Tolerant Inputs
The MC74LVX573 is an advanced high speed CMOS octal latch with 3-state outputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. This 8-bit D-type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state.
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20
* * * * * * * * *
High Speed: tPD = 6.4 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available*
LVX573 AWLYYWW SOIC-20 DW SUFFIX CASE 751D
1
LVX 573 ALYW TSSOP-20 DT SUFFIX CASE 948E
VCC 20
O0 19
O1 18
O2 17
O3 16
O4 15
O5 14
O6 13
O7 12
LE 11 SOEIAJ-20 M SUFFIX CASE 967 LVX573 AWLYWW
1 OE
2 D0
3 D1
4 D2
5 D3
6 D4
7 D5
8 D6
9 D7
10 GND
Figure 1. 20-Lead Pinout (Top View)
A WL, L Y, YY W, WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 3
Publication Order Number: MC74LVX573/D
MC74LVX573
OE LE 1 11 2 nLE D nLE D nLE D nLE D nLE D nLE D nLE D nLE D Q 19 O0
Table 1. PIN NAMES
Pins OE LE D0-D7 O0-O7 Function Output Enable Input Latch Enable Input Data Inputs 3-State Latch Outputs
D0
D1
3
Q
18
O1 OE
INPUTS LE H H L L L L H H L L Dn H L h l X X H L h l
OUTPUTS On H L H L NC Z Z Z Z Z OPERATING MODE Transparent (Latch Disabled); Read Latch Latched (Latch Enabled) Read Latch Hold; Read Latch Hold; Disabled Outputs Transparent (Latch Disabled); Disabled Outputs Latched (Latch Enabled); Disabled Outputs
D2
4
Q
17
O2
L L L L
D3
5
Q
16
O3
L H
D4
6
Q
15
H H O4 H H
D5
7
Q
14
O5
D6
8
Q
13
O6
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition; NC = No Change, State Prior to the Latch Enable High-to-Low Transition; X = High or Low Voltage Level or Transitions are Acceptable; Z = High Impedance State; For ICC Reasons DO NOT FLOAT Inputs.
D7
9
Q
12
O7
Figure 2. Logic Diagram
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MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage -0.5 to +7.0 -0.5 to +7.0 Vout IIK DC Output Voltage -0.5 to VCC +0.5 -20 20 25 75 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation 180 mW C Tstg Storage Temperature -65 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
Symbol
Dt/DV
tOSHL tOSLH
tPLH, tPHL
tPLH, tPHL
tPLZ, tPHZ
tPZL, tPZH
VOH
VCC
Vout
VOL
VIH
ICC
IOZ
VIL
Vin
TA
Iin
Output-to-Output Skew (Note 1)
Output Disable Time OE to O
Output Enable Time OE to O
Propagation Delay D to O
Propagation Delay LE to O
Quiescent Supply Current
Maximum 3-State Leakage Current
Input Leakage Current
Low-Level Output Voltage (Vin = VIH or VIL)
High-Level Output Voltage (Vin = VIH or VIL)
Low-Level Input Voltage
High-Level Input Voltage
Input Rise and Fall Time
Operating Temperature, All Package Types
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
Parameter
VCC = 2.7 V VCC = 3.3 0.3 V
VCC = 3.3 0.3 V RL = 1 kW
VCC = 2.7 V RL = 1 kW
VCC = 3.3 0.3 V RL = 1 kW
VCC = 2.7 V RL = 1 kW
VCC = 3.3 0.3 V
VCC = 2.7 V
VCC = 3.3 0.3 V
VCC = 2.7 V
Parameter
IOL = 50 mA IOL = 50 mA IOL = 4 mA
IOH = -50 mA IOH = -50 mA IOH = -4 mA
Vin = VCC or GND
Vin = VIL or VIH Vout = VCC or GND
Vin = 5.5 V or GND
Test Conditions
Test Conditions
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MC74LVX573
3 CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF VCC V 3.6 3.6 3.6 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.6 2.0 3.0 3.6 1.9 2.9 2.58 Min Min 1.5 2.0 2.4 TA = 25C TA = 25C 7.8 10.3 7.6 10.1 8.2 10.7 10.1 12.1 Typ Typ 6.1 8.6 5.9 8.4 6.4 8.9 0.0 0.0 2.0 3.0 9.7 13.2 9.3 12.8 0.1 0.1 0.36 13.6 19.1 15.0 18.5 14.5 18.0 10.1 13.6 15.6 19.1 Max Max 0.2 5 0.1 4.0 0.5 0.8 0.8 1.5 1.5 Min -40 2.0 0 0 0 TA = - 40 to 85C TA = - 40 to 85C 1.9 2.9 2.48 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 2.0 2.4 Max VCC +85 100 5.5 3.6 0.1 0.1 0.44 11.0 14.5 15.5 22.0 12.0 15.5 18.5 22.0 17.5 21.0 12.0 15.5 18.5 22.0 Max 40.0 2.5 1.0 Max 0.5 0.8 0.8 1.5 1.5 ns/V Unit Unit Unit mA mA mA C ns ns ns ns ns V V V V V V V
MC74LVX573
III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
CAPACITIVE CHARACTERISTICS
TA = 25C Typ 4 6 TA = - 40 to 85C Min Max 10 Symbol Cin Parameter Min Max 10 Unit pF pF pF Input Capacitance Cout CPD Maximum 3-State Output Capacitance Power Dissipation Capacitance (Note 2) 29 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V, Measured in SOIC Package)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.5 -0.5 Max 0.8 -0.8 2.0 0.8 Unit V V V V
TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)
TA = 25C Symbol tw(h) tsu th Parameter Minimum Pulse Width, LE Minimum Setup Time, D to LE Minimum Hold Time, D to LE Test Conditions VCC = 2.7 V VCC = 3.3 0.3 V VCC = 2.7 V VCC = 3.3 0.3 V VCC = 2.7 V VCC = 3.3 0.3 V Typ Limit 6.5 5.0 5.0 3.5 1.5 1.5 TA = - 40 to 85C Limit 7.5 5.0 5.0 3.5 1.5 1.5 Unit ns ns ns
ORDERING INFORMATION
Device MC74LVX573DWR2 MC74LVX573DWR2G MC74LVX573DT MC74LVX573DTR2 MC74LVX573M MC74LVX573MG MC74LVX573MEL MC74LVX573MELG Package SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel 50 Units / Rail 50 Units / Rail 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX573
SWITCHING WAVEFORMS
VCC D tPLH O 50% VCC O 50% VCC 50% tPHL GND tw LE 50% tPLH tPHL VCC GND
Figure 3.
Figure 4.
OE
VCC 50% tPZL O 50% VCC tPZH O 50% VCC tPHZ VOL -0.3 V HIGH IMPEDANCE tPLZ GND HIGH IMPEDANCE VOL +0.3 V LE D 50% tsu th 50% VALID
VCC GND VCC GND
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Propagation Delay Test Circuit
Figure 8. 3-State Test Circuit
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MC74LVX573
PACKAGE DIMENSIONS
SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
20X
L
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74LVX573
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX573
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MC74LVX573/D

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